The present invention relates in general to a high voltage lateral double diffused metal oxide semiconductor (LDMOS) transistor, and more particularly, to a high voltage LDMOS transistor in which the on-resistance of a transistor is reduced without a reduction in the breakdown voltage.
In order to achieve high switching speed, the on-resistance of the high voltage LDMOS transistor must be low. In general, the on-resistance of the LDMOS transistor is primarily determined by the channel resistance and by the drift region resistance. In the case of high voltage LDMOS transistor, the on-resistance is governed primarily by the drift region resistance. Thus, in order to reduce the on-resistance of the high voltage LDMOS transistor, the drift region resistance must be reduced. To reduce the drift region resistance, the concentration of impurities in the drift region must be increased. However, increasing the concentration of the impurities in the drift region results in lower breakdown voltage. Thus, there is a trade off relation between the on-resistance and the breakdown voltage of the device.
FIG. 1 is a cross-sectional view of a conventional high voltage LDMOS transistor. An n−-type epitaxial layer 12 is formed on a p−-type substrate 10. An n−-type buried layer 13 is extends into both p−-type substrate 10 and n−-type epitaxial layer 12. An n−-type well region 14 is formed in n−-type epitaxial layer 12, and extends over n−-type buried layer 13. A p−-type body region 15 is formed in n−-type well region 14. An n+-type source region 16 and a p+-type body-contact region 17 are formed in p−-type body region 15. A p+-type region 18 extends from below n+-type source region 16 and a p+-type body-contact region 17 through p−-type body region 15, terminating in n−-type well region 14. An n+-type drain region 19 is formed in n−-type well region 14.
A gate insulating layer 20 extends over n−-type well region 14 and a surface portion of p−-type body region 15. A gate conductive layer 21 extends over gate insulating layer 20 and an upper portion of a local oxidation of silicon (LOCOS) oxide layer 22. A source electrode 23 is in contact with n+-type source region 16 and p+-type source contact region 17, and a drain electrode 24 is in contact with n+-type drain region 19. Gate conductive layer 21, source electrode 23, and drain electrode 24 are electrically isolated from one another by an interlayer dielectric (ILD) film 25.
FIG. 2 shows the electric field profile in the high voltage LDMOS transistor of FIG. 1 when a reverse bias is applied across the drain-source terminals. Same reference numerals as those in FIG. 1 denote same regions or layers. Upon applying a reverse bias across the drain-source electrodes, a depletion region extends out from the junction between p−-type body region 15 and n−-type well region 14, and electric field potential lines 26 are formed in the depletion region. If the depletion region extends out beyond a critical limit, breakdown occurs. If the concentration of impurities in n−-type well region 14 is increased in order to obtain a lower on-resistance, the depletion region reaches the critical limit at lower drain-source voltages. That is, breakdown occurs with lower electric field intensity, and thus the transistor breakdown voltage is reduced.
Thus, a LDMOS transistor wherein the on-resistance can be reduced without adversely impacting the breakdown voltage is desirable.